1. Field of Invention
The present invention relates to a type of non-volatile memory. More particularly, the present invention relates to a type of non-volatile memory cell capable of working at a low power but having a high efficiency.
2. Description of Related Art
Most erasable programmable read-only-memory (EPROM), electrically erasable programmable read-only-memory (EEPROM) and flash memory all have similar structures that resemble the one shown in FIG. 1. These memories typically include a control gate 103 and a channel 101 with a floating gate 102 sandwiched between the two. The floating gate 102 is a conductive layer normally fabricated using polysilicon material. The floating gate layer 102 is a continuous thin film having a thickness of about 1200 .ANG., and is generally formed using a chemical vapor deposition process. The floating gate 102 is an electrically isolated structure not attached to any electrodes or power source and is generally surrounded by insulation material. Data can be written into the memory by injection hot electrons through the channel 101 or the substrate 100 into the floating gate layer 102. The flow of hot electrons can be reversed sending the trapped electrons out of the floating gate layer 102 to erase the stored data.
The method of writing data into a non-volatile EPROM cell in general includes setting up an electric field across a Si/SiO.sub.2 barrier layer to attract channel electrons or supplying to the electrons with enough energy to overcome the barrier. Consequently, the threshold voltage of the memory cell is increased. The variation of threshold voltage caused by the change in stored electric charges within the floating gate layer 102 can represent a logic state of "0" and "1", respectively. To erase stored data from an EPROM cell, a high electric field is set up between the source terminal 104 and the gate control 103 (source terminal being positive) with the drain terminal disconnected from any voltage source.
Therefore, electric trapped charges in the floating gate layer 102 can now penetrate a neighboring barrier layer, and so the electric charges are removed. After the removal of electric charges within the floating gate 102, threshold voltage of the transistor inside the memory cell unit drops. In normal circumstances, data charges leaking from the floating gate 102 to the source region 104, the drain region 105 and the substrate 100, respectively, must be prevented for the correct reading of data and for long data retention period. One consequence is that the tunneling oxide layer 106 must not be too thin. Otherwise, the electric trapped charges can easily leak away.
On the other hand, having a thick tunneling oxide layer 106 is not altogether beneficial to the operation of the memory, either. This is because a higher writing or erasing voltage must be supplied to the hot electrons in the channel before the electrons can jump across the barrier layer between the floating gate 102 and the channel. The higher voltage not only consumes more electric power, and degradation caused by the hot carriers within the tunneling oxide layer 106 may also occur, as well.
As dimensions of memory devices continue to shrink, thickness of the tunneling oxide layer has to be reduced correspondingly. On the positive side, having a thinner tunneling oxide layer increases data writing and erasing efficiency as well as speed. However, a thin tunneling oxide layer can easily result in the breakdown of the oxide layer. In other words, the oxide layer can be damaged by energetic carriers leading to an increase in leakage current from the floating gate. Furthermore, the leakage current can act in reverse to prevent the flow of electrons into the floating gate in a memory-write operation. Consequently, memory-write operations may take longer. Subjected to correct data reading and data retention constraints, the tunneling oxide layer preferably has a thickness of more than 70 .ANG..
In light of the foregoing, there is a need to improve the power consumption, efficiency, reading accuracy and data retention period of a non-volatile EPROM cell.